Two Fabs in Construction, One Awaiting Government Approval

When Taiwan Semiconductor Manufacturing Co. (TSMC) is prepping to roll out an all-new process technology, it usually builds a new fab to meet demand of its alpha customers and then either adds capacity by upgrading existing fabs or building another facility. With N2 (2nm-class), the company seems to be taking a slightly different approach as it is already constructing two N2-capable fabs and is awaiting for a government approval for the third one.

We are also preparing our N2 volume production starting in 2025,” said Mark Liu, TSMC’s outgoing chairman, at the company’s earnings call with financial analysts and investors. “We plan to build multiple fabs or multiple phases of 2nm technologies in both Hsinchu and Kaohsiung science parks to support the strong structural demand from our customers. […] “In the Taichung Science Park, the government approval process is ongoing and is also on track.”

TSMC is gearing up to construct two fabrication plants capable of producing N2 chips in Taiwan. The first fab is planned to be located near Baoshan in Hsinchu County, neighboring its R1 research and development center, which was specifically build to develop N2 technology and its successor. This facility is expected to commence high-volume manufacturing (HVM) of 2nm chips in the latter half of 2025. The second N2-capable fabrication plant by is to be located in the Kaohsiung Science Park, part of the Southern Taiwan Science Park near Kaohsiung. The initiation of HVM at this plant is projected to be slightly later, likely around 2026.

In addition, the foundry is working to get government approvals to build a yet another N2-capable fab in the Taichung Science Park. If the company starts to construct this facility in 2025, the fab could go online as soon as in 2027.

With three fabs capable of making chis using its 2nm process technologies, TSMC is poised to offer vast 2nm capacity for years to come.

TSMC expects to start HVM using its N2 process technology that uses gate-all-around (GAA) nanosheet transistors around the second half of 2025. TSMC’s 2nd generation 2nm-class process technology — N2P — will add backside power delivery. This technology will be used for mass production in 2026.

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